The present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic package that includes an integrated circuit (IC) die or an IC package coupled to a substrate with multiple-zone interconnects, and to manufacturing methods related thereto.
Integrated circuits (ICs) are typically assembled into electronic packages by physically and electrically coupling one or more ICs to a substrate made of organic or ceramic material. One or more IC packages can be physically and electrically coupled to a substrate such as a printed circuit board (PCB) or motherboard to form an xe2x80x9celectronic assemblyxe2x80x9d. The xe2x80x9celectronic assemblyxe2x80x9d can be part of an xe2x80x9celectronic systemxe2x80x9d. An xe2x80x9celectronic systemxe2x80x9d is broadly defined herein as any product comprising an xe2x80x9celectronic assemblyxe2x80x9d. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the packaging of ICs, where each new generation of packaging must provide increased performance and reliability while generally being smaller or more compact in size. As market forces drive equipment manufacturers to produce electronic systems with increased complexity, performance, and reliability, and with decreased size, IC packaging accordingly also needs to support these requirements.
An IC substrate may comprise a number of metal layers selectively patterned to provide metal interconnect lines (referred to herein as xe2x80x9ctracesxe2x80x9d), and one or more electronic components mounted on one or more surfaces of the substrate. The electronic component or components are functionally connected to other elements of an electronic system through a hierarchy of electrically conductive paths that include the substrate traces. The substrate traces typically carry signals that are transmitted between the electronic components, such as ICs, of the system.
Some ICs have a relatively large number of input/output (I/O) terminals (also called xe2x80x9clandsxe2x80x9d), as well as a large number of power and ground terminals or lands. I/O terminals are typically located near the periphery of the IC, whereas power supply terminals are typically located in a central region of the IC.
Surface mount technology (SMT) is a widely known technique for coupling ICs to a substrate. One of the conventional methods for surface-mounting an IC on a substrate is called xe2x80x9ccontrolled collapse chip connectxe2x80x9d (C4). In fabricating a C4 package, the electrically conductive terminals of an IC component are soldered directly to corresponding terminals on the surface of the substrate using reflowable solder bumps or balls. The C4 process is widely used because of its robustness and simplicity. However, C4 structures may not accommodate thermally induced stresses occurring during thermal cycling, particularly those arising from the coefficient of thermal expansion (CTE) mismatch between the die material and substrate material, especially at high densities of input/output (I/O) terminals on large ICs.
In addition to CTE mismatch problems arising within the die-to-package interconnect, CTE mismatch can also cause reliability problems at higher levels of IC packaging, such as between an IC package and a PCB substrate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for IC packaging, whether of unpackaged or packaged dies, and methods of fabricating such IC packaging that can accommodate thermal stresses while still providing good mechanical and electrical connections between the IC terminals (or IC package terminals) and the substrate terminals.